1. Field of the Invention
This invention relates to, for example, an electronic control apparatus into which two CPUs (microprocessor) used for control of an engine for automobile are built, and particularly to an improved vehicle built-in electronic control apparatus suitable for communicating multiple data between a main CPU and a sub CPU using a serial communication function.
2. Description of the Related Art
A vehicle built-in electronic control apparatus comprising a main CPU for performing the whole control, a sub CPU for performing control targeted for a specific function and a serial communication function for conducting various data communications between both the CPUs is publicly known.
For example, in xe2x80x9cengine control apparatusxe2x80x9d disclosed in JP-A-10-89141, there is proposed means in which control data (control constant) of a sub microcomputer (sub CPU) is stored in flash memory (first nonvolatile memory) of a main microcomputer (main CPU) and is transferred to RAM memory of the sub microcomputer through serial communication at the time of starting of control and also data of the flash memory can be rewritten from an external writing device (external tool) and thus the control data of the sub microcomputer is indirectly written and set from the external writing device.
On the other hand, in xe2x80x9cdata communication apparatusxe2x80x9d disclosed in JP-A-5-128065, there is described an engine control apparatus for sending digital data between a master CPU and a slave CPU using a clock signal for communication and a handshake signal, and the digital data is considered as various control information occurring in operation of the engine control apparatus.
In addition, as means related to the operation monitoring in an engine control apparatus using two CPUs connected through data buses, in xe2x80x9coperation monitoring method of two CPUsxe2x80x9d disclosed in, for example, JP-A-5-81222, there is proposed means in which runaway monitoring of a sub CPU is performed by a main CPU and runaway monitoring of the main CPU is performed by hardware by means of a watch dog timer circuit.
In the runaway monitoring, there is the means for resetting the CPU at the time of abnormal occurrence to restart it, and in xe2x80x9cdigital processing apparatusxe2x80x9d disclosed in JP-A-8-339308, there is proposed means in which an abnormal occurrence is stored and it is set to a full stop state impossible to restart a CPU in normal reset and this full stop state is released by again turning on an operating power source.
In such conventional arts described above, in JP-A-10-89141, serial communication means is used for the purpose of downloading the control constant from the main microcomputer to the sub microcomputer in a batch manner at the time of starting operation, and other limited signals are directly passed from the sub microcomputer to the main microcomputer.
Also, in JP-A-5-128065, there is a problem in that there are no degrees of freedom for mutually communicating various data between the master CPU and the slave CPU.
Further, in JP-A-5-81222, only the restarting of the CPU at the time of runaway occurrence of the CPU may leave a problem, and on the contrary, the full stop of the CPU as disclosed in JP-A-8-339308 also causes a problem.
A first object of the invention is to provide serial communication means capable of transferring control constants at the time of starting operation or freely intercommunicating various data in operation by improving the problems as described above in a vehicle built-in electronic control apparatus comprising a main CPU and a sub CPU with shared functions.
A second object of the invention is to provide an additional function for performing runaway monitoring and communication abnormal monitoring of each CPU to make safe recovery from an abnormality in a vehicle built-in electronic control apparatus comprising two CPUs as described above.
To achieve the above objects, a vehicle built-in electronic control apparatus according to the invention, which is a vehicle built-in electronic control apparatus fed from a vehicle built-in battery through a power switch, comprises a main CPU including first nonvolatile memory in which at least first control programs and control constants in correspondence with a controlled vehicle are written from an external tool, first RAM memory for calculation processing and first input/output ports, a sub CPU including second nonvolatile memory in which second control programs are written, second RAM memory for calculation processing and second input/output ports, and a serial-parallel converter for full duplex two-way serial communication for mutually conducting data communications between the main CPU and the sub CPU in operation of the controlled vehicle, and at the time of starting operation of the controlled vehicle, apart of the control constants stored in the first nonvolatile memory is transferred to the second RAM memory through the serial-parallel converter for the serial communication and the sub CPU performs predetermined calculation based on the contents of the second control programs of the second nonvolatile memory and the contents of the control constants transferred to the second RAM memory.
Also, there are provided a second power terminal for feeding power to each the CPU and the memory, and a first power terminal which is connected to the vehicle built-in battery without intervention of the power switch and feeds power to at least the second RAM memory, and even when the power switch is broken, the contents of at least the second RAM memory are held by the feeding from the first power terminal.
Also, there is further provided third nonvolatile memory, and the contents of the second RAM memory are saved in the third nonvolatile memory at the time of breaking the power switch and are transferred from the third nonvolatile memory to the second RAM memory at the time of again turning on the power switch.
Also, the main CPU and the sub CPU comprise control constant sending means for sending the control constants stored in the first nonvolatile memory to the sub CPU when the contents of the first nonvolatile memory have been changed at the time of starting operation of the controlled vehicle, direct request means capable of performing an interruption request of data sending from the sending side CPU to the receiving side CPU when the contents of the first nonvolatile memory have not been changed, irregular data sending means for sending the sending data as irregular data in the case that the interruption request by this direct request means is absent but there is a need for interruption sending from the sending side CPU to the receiving side CPU and the case that there is no need for the interruption sending but a data request from the receiving side CPU to the sending side CPU is present, and regular data sending means for regularly sending the sending data as regular data in the case that all the interruption request by the direct request means, the need for the interruption sending and the data request from the receiving side CPU to the sending side CPU are absent.
Also, a direct memory access controller is connected to at least one data bus of the sides of the main CPU or the sub CPU and sending data received through the serial-parallel converter for the serial communication is stored in the receiving side RAM memory without intervention of the receiving side CPU.
Also, the main CPU and the sub CPU comprise sum check means for making an error check of received data by the serial-parallel converter for the serial communication in the receiving side CPU, resending request means for requesting the resending of the received data to the sending side CPU if this sum check means determines that an error is present in the received data, and time-out check means for determining whether an interval between sending start time from the sending side CPU to the receiving side CPU and verification answer receiving time of the received data from the sum check means is within a predetermined time interval or not.
Also, the main CPU comprises reset output means for monitoring a watch dog signal of the sub CPU and a time-out check result of communication and generating a reset pulse output at the time of operation abnormality of the sub CPU to restart the sub CPU, and a watch dog timer circuit for monitoring a watch dog signal of the main CPU and generating a reset pulse output at the time of operation abnormality to restart the main CPU.
Also, there are provided a memory element reset by breaking or again turning on the power switch while storing generation of the reset pulse output, an output stop circuit for stopping a driving of a part of loads in response to an operation of this memory element, and alarm and indication means for giving an alarm and indication of operation abnormality in response to the operation of the memory element.